(1) Field of the Invention
The present invention relates to a nonvolatile random access memory device, more particularly, it relates to an improvement of a non-volatile random access memory device having a plurality of memory cells, each of the memory cells comprising a volatile static type random access memory cell and a non-volatile memory cell including a memory transistor having a floating gate.
Such a non-volatile random access memory device not only carries out data read/write operations at a high speed, due to the static type random access memory cell, but also holds the written data while the power source supplied to the memory cells is cut OFF, memory devices are generally used in the field of, for example, electronic musical instruments, IC cards, facsimiles, telephones, wherein stored date must be held while the power source for the memory cells is cut OFF and the stored data can be rewritten as new data when the above power source is made ON.
(2) Description of the Related Art
Generally, the conventional non-volatile random access memory device of this type has a plurality of memory cells, each of which comprises a volatile static type random access memory cell including a flip-flop circuit and a non-volatile memory cell including a tunnel capacitor and a memory transistor having a floating gate.
Predetermined data is written from bit lines to the flip-flop circuit in the volatile memory cell, and the data is read out from the flip-flop circuit to the bit lines, when a corresponding word line is selected.
The non-volatile memory cell stores the data from the corresponding volatile memory cell before the power source applied to the volatile memory cell is cut OFF and recalls the stored data to the volatile memory cell when the power source is again applied to the volatile memory cell.
When storing the data from the volatile memory cell to the non-volatile memory cell, electrons are tunneled from an electrode of the tunnel capacitor connected to the floating gate to an opposing electrode of the tunnel capacitor, or vice versa, through an insulator film of the tunnel capacitor to which an electric field having a predetermined high intensity is applied, in accordance with the data from the corresponding volatile memory cell. Accordingly, the potential at the floating gate in the non-volatile memory cell becomes positive (i.e., positively charged state) or negative (i.e., negatively charged state), in accordance with the data from the corresponding volatile memory cell. Namely, the data from the volatile memory cell is stored to the corresponding non-volatile memory cell as a predetermined potential (i.e., in a predetermined charged state) at the floating gate.
Next when recalling the data stored in the non-volatile memory cell to the volatile memory cell, the flip-flop circuit in the volatile memory cell is initially preset at a predetermined state. At this time, a recall signal is supplied to the non-volatile memory cell (i.e., to a gate of a recall transistor connected to the memory transistor having the floating gate in series), and if the potential at the floating gate is negative, the memory transistor is cut-OFF, and thus the flip-flop circuit in the volatile memory cell is maintained in the above preset state, even if the recall signal is supplied to the recall transistor. On the other hand, if the potential at the floating gate is positive, the memory transistor is made ON, and thus the data preset in the flip-flop circuit is inverted in accordance with the data recalled from the corresponding non-volatile memory cell through the memory transistor which is ON and the recall transistor to which the recall signal is supplied. As a result, the data corresponding to the potential at the floating gate (i.e., the data corresponding to the ON or OFF state of the memory transistor) is recalled from the non-volatile memory cell to the flip-flop circuit in the volatile memory cell.
Therefore, in the memory device of this type, the above-mentioned data storing operation and data recalling operation between the volatile memory cell and the non-volatile memory cell are necessarily repeated many times, in accordance with users' commands. In this connection, the number of times that the repetition of the above data storing operation and data recalling operation can be carried out is guaranteed by the maker, but the above non-volatile memory cell may deteriorate due to a repetition of operations, although within the above guaranteed number, because of a defect therein, particularly in the insulator film of the tunnel capacitor. Namely, when storing the data from the volatile memory cell to the non-volatile memory cell, a predetermined high potential is applied between both electrodes of the tunnel capacitor, and thus a problem arises in that the insulator film of the tunnel capacitor is deteriorated or destroyed in accordance with the increase of the above number of operations, and further, the above charges having a predetermined polarity at the floating gate tend to leak through the insulator film of the tunnel capacitor, with the result that the value of the above potential at the floating gate changes to an erroneous value which does not correspond to the data to be stored in the non-volatile memory cell.
In view of the above-mentioned problem, attempts have been made to provide an error check and correct circuit (so-called ECC circuit) together with the above memory device on the same chip. But, in such a memory device, the chip area needed for the ECC circuit occupies a remarkably large part of the entire chip area, particularly when the bit number constituting one word data is relatively small, and further, the entire circuit construction of the memory device becomes complicated even when only one erroneous bit included in the one word output data is detected and corrected, as described below in detail.